ICS 2024: International Conference on Supercomputing

June 4-7, 2024

International Exchange Hall, Kyoto University, Kyoto, Japan

Workshops (June 4th, 13:00 - 17:30 JST)

Those who register for the main conference can attend the workshop free of charge. Please register first, as you will not be able to participate in workshops if you have not registered.

Workshops will be held in the International Science Innovation Building (Buildings numbered 69), with the registration desk in Conference Room 1 on the 1st floor of the building. If you have already completed your registration and payment through the registration site, please proceed to this desk upon arrival to check in before participating in workshops. Please note that the registration desk will be moved to the entrance of the International Exchange Hall, 2nd floor, Clock Tower Centennial Hall (Buildings numbered 3) from June 5th.

ICS2024 will hold the following workshops:

  • QCCC: International Workshop on Quantum Classical Cooperative Computing
  • Location:

    Room 1 - Conference Rooms 5a/5b, located on the 5th floor


    The Third International Workshop on Quantum Classical Cooperative Computing (QCCC 2024) aims to explore innovative approaches in quantum-classical cooperative computing to enhance effectiveness and scalability of quantum computing in NISQ platforms. It will focus on how classical computing can improve NISQ device execution, scalability, and noise compensation, with emphasis on existing platforms like IBM-Q, IonQ, and Rigetti. Topics include quantum-classical hybrid algorithms, quantum error correction, and more.

  • 2nd Workshop on FPGA Technologies for Adaptive Computing (FTAC 2024)
  • Location:

    Room 2 - Meeting Rooms E/F, located on the 5th floor


    FTAC 2024 aims to discuss novel ideas and methodologies in FPGA technologies to meet the increasing demands of High-Performance Computing (HPC) and Artificial Intelligence (AI) for efficient computing systems. Topics of interest include FPGA acceleration for HPC applications, innovative FPGA technologies, network-on-chip, optimized soft processors, rapid-prototyping, and educational systems for FPGA acceleration. The workshop encourages submissions of extended abstracts for innovative early-stage ideas, with proceedings provided exclusively to attendees.